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| 19-0513; Rev 0; 5/06 KIT ATION EVALU ABLE AVAIL High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor General Description Features 100Msps Conversion Rate -82dBFS Noise Floor Excellent Low-Noise Characteristics SNR = 79.4dB at fIN = 10MHz SNR = 79dB at fIN = 70MHz Excellent Dynamic Range (SFDR1/SFDR2) 93.2dBc/102.5dBc at fIN = 10MHz 82.1dBc/97.7dBc at fIN = 70MHz Less than 0.1ps Sampling Jitter 1275mW Power Dissipation 2.56VP-P Fully Differential Analog Input Voltage Range CMOS-Compatible Two's-Complement Data Output Separate Data Valid Clock and Over-Range Outputs Flexible Input Clock Buffer Small 56-Pin, 8mm x 8mm x 0.8mm Thin QFN Package EV Kit Available for MAX19588 (Order MAX19588EVKIT) MAX19588 The MAX19588 is a 3.3V, high-speed, high-performance analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) and a 16-bit converter core. The MAX19588 is optimized for multichannel, multimode receivers, which require the ADC to meet very stringent dynamic performance requirements. With a -82dBFS noise floor, the MAX19588 allows for the design of receivers with superior sensitivity requirements. At 100Msps, the MAX19588 achieves a 79dB signal-tonoise ratio (SNR) and an 82.1dBc/97.7dBc single-tone spurious-free dynamic range performance (SFDR1/ SFDR2) at fIN = 70MHz. The MAX19588 is not only optimized for excellent dynamic performance in the 2nd Nyquist region, but also for high-IF input frequencies. For instance, at 130MHz, the MAX19588 achieves an 82.3dBc SFDR and its SNR performance stays flat (within 2.3dB) up to 175MHz. This level of performance makes the part ideal for high-performance digital receivers. The MAX19588 operates from a 3.3V analog supply voltage and a 1.8V digital voltage, features a 2.56VP-P full-scale input range, and allows for a guaranteed sampling speed of up to 100Msps. The input track-and-hold stage operates with a 600MHz full-scale, full-power bandwidth. The MAX19588 features parallel, low-voltage CMOScompatible outputs in two's-complement output format. The MAX19588 is manufactured in an 8mm x 8mm, 56-pin thin QFN package with exposed paddle (EP) for low thermal resistance, and is specified for the extended industrial (-40C to +85C) temperature range. Ordering Information PART MAX19588ETN-D MAX19588ETN+D TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE PKG CODE 56 Thin QFN-EP* T5688-2 56 Thin QFN-EP* T5688-2 Applications Cellular Base-Station Transceiver Systems (BTS) Wireless Local Loop (WLL) +Denotes lead-free package. D = Dry pack. *EP = Exposed paddle. Pin Configuration DGND DGND DVDD DVDD D8 D7 D6 D5 D4 D3 D2 D1 42 41 40 39 38 37 36 35 34 33 32 31 30 29 D9 43 D10 44 28 AGND 27 REFIN 26 REFOUT 25 AVDD 24 AVDD 23 AVDD 22 AGND D0 Multicarrier Receivers Multistandard Receivers E911 Location Receivers High-Performance Instrumentation Antenna Array Processing TOP VIEW D11 45 D12 46 D13 47 D14 48 D15 49 DAV 50 DVDD 51 DGND 52 DOR 53 N.C. 54 AVDD 55 AVDD 56 1 AVDDA 2 AVDDA 3 AGND 4 CLKP 5 CLKN 6 AGND 7 AGND 8 AGND 9 AGND 10 11 12 13 14 AGND AGND AGND INP INN EP MAX19588 DVDD 21 AGND 20 AGND 19 AVDD 18 AVDD 17 AVDD 16 N.C. 15 N.C. THIN QFN 8mm x 8mm ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 ABSOLUTE MAXIMUM RATINGS AVDD, AVDDA to AGND ........................................ -0.3V to +3.6V DVDD to DGND..................................................... -0.3V to +2.4V AGND to DGND.................................................... -0.3V to +0.3V INP, INN, CLKP, CLKN, REFP, REFN, REFIN, REFOUT to AGND....................-0.3V to (AVDD + 0.3V) D0-D15, DAV, DOR to GND ....................-0.3V to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 56-Pin Thin QFN-EP (derate 47.6mW/C above +70C) .........................3809.5mW Operating Temperature Range ..........................-40C to +85C Thermal Resistance JA ..................................................21C/W Thermal Resistance JC .................................................0.6C/W Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = AVDDA = 3.3V, DVDD = 1.8V, AGND = DGND = 0, internal reference, INP and INN driven differentially, CLKP and CLKN driven differentially, CL = 5pF at digital outputs (D0-D15, DOR), CL = 15pF for DAV, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 1) PARAMETER DC ACCURACY Resolution Offset Error Gain Error ANALOG INPUTS (INP, INN) Input Voltage Range Common-Mode Voltage Differential Input Resistance Differential Input Capacitance Full-Power Analog Bandwidth VDIFF VCM RIN CIN BW-3dB -3dB rolloff for FS Input Fully differential input, VIN = VINP - VINN Internally self-biased 2.56 2.4 10 20% 7 600 1.28 10% 1.28 VP-P V k pF MHz N VOS GE 0 -3.5 16 10 20 +3.5 Bits mV %FS SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE INPUT/OUTPUT (REFIN, REFOUT) Reference Input Voltage Range REFIN V V Reference Output Voltage REFOUT DYNAMIC SPECIFICATIONS (fCLK = 100Msps) Thermal Plus Quantization Noise Floor NF AIN < -35dBFS fIN = 10MHz, AIN = -2dBFS fIN = 70MHz, AIN = -2dBFS, TA = +25C Signal-to-Noise Ratio (First 4 Harmonics Excluded) (Note 2) SNR fIN = 70MHz, AIN = -2dBFS fIN = 105MHz, AIN = -2dBFS fIN = 130MHz, AIN = -2dBFS fIN = 168MHz, AIN = -2dBFS 77.5 75.3 -82 79.4 79 79 78.3 77.5 76.6 dBFS dB 2 _______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor ELECTRICAL CHARACTERISTICS (continued) (AVDD = AVDDA = 3.3V, DVDD = 1.8V, AGND = DGND = 0, internal reference, INP and INN driven differentially, CLKP and CLKN driven differentially, CL = 5pF at digital outputs (D0-D15, DOR), CL = 15pF for DAV, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS fIN = 10MHz, AIN = -2dBFS fIN = 70MHz, AIN = -2dBFS, TA = +25C Signal-to-Noise Plus Distortion (Note 2) SINAD fIN = 70MHz, AIN = -2dBFS fIN = 105MHz, AIN = -2dBFS fIN = 130MHz, AIN = -2dBFS fIN = 168MHz, AIN = -2dBFS fIN = 10MHz, AIN = -2dBFS fIN = 70MHz, AIN = -2dBFS, TA = +25C fIN = 70MHz, AIN = -2dBFS fIN = 105MHz, AIN = -2dBFS fIN = 130MHz, AIN = -2dBFS fIN = 168MHz, AIN = -2dBFS fIN = 10MHz, AIN = -2dBFS fIN = 70MHz, AIN = -2dBFS, TA = +25C fIN = 70MHz, AIN = -2dBFS fIN = 105MHz, AIN = -2dBFS fIN = 130MHz, AIN = -2dBFS fIN = 168MHz, AIN = -2dBFS fIN = 10MHz, AIN = -2dBFS Second-Order Harmonic Distortion fIN = 70MHz, AIN = -2dBFS, TA = +25C fIN = 70MHz, AIN = -2dBFS fIN = 105MHz, AIN = -2dBFS fIN = 130MHz, AIN = -2dBFS fIN = 168MHz, AIN = -2dBFS fIN = 10MHz, AIN = -2dBFS fIN = 70MHz, AIN = -2dBFS, TA = +25C fIN = 70MHz, AIN = -2dBFS fIN = 105MHz, AIN = -2dBFS fIN = 130MHz, AIN = -2dBFS fIN = 168MHz, AIN = -2dBFS Third-Order Intermodulation Distortion Two-Tone SFDR CONVERSION RATE Maximum Conversion Rate Minimum Conversion Rate Aperture Jitter fCLKMAX fCLKMIN tJ 85 100 20 MHz MHz fsRMS IM3 TTSFDR fIN1 = 65.1MHz, AIN1 = -8dBFS fIN2 = 70.1MHz, AIN2 = -8dBFS fIN1 = 65.1MHz, fIN2 = 70.1MHz, -100dBFS < AIN < -10dBFS 90.4 85 79.6 79.3 75 73.5 MIN TYP 79 77.1 77.1 77.1 75.8 70.8 93.2 82.1 82.1 86.6 82.3 75.4 102.5 97.7 97.7 94.2 94.1 91.5 -94.3 -93 -93 -88 -82.3 -77.6 -94.3 -82.1 -82.1 -87.4 -92.5 -75.4 -87.7 98 dBc dBFS -79.6 -79.3 -83 -78.3 dB MAX UNITS MAX19588 Spurious-Free Dynamic Range (Worst Harmonic, 2nd and 3rd) SFDR1 dBc Spurious-Free Dynamic Range (Worst Harmonic, 4th and Higher) (Note 2) SFDR2 dBc HD2 dBc Third-Order Harmonic Distortion HD3 dBc _______________________________________________________________________________________ 3 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 ELECTRICAL CHARACTERISTICS (continued) (AVDD = AVDDA = 3.3V, DVDD = 1.8V, AGND = DGND = 0, internal reference, INP and INN driven differentially, CLKP and CLKN driven differentially, CL = 5pF at digital outputs (D0-D15, DOR), CL = 15pF for DAV, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 1) PARAMETER CLOCK INPUTS (CLKP, CLKN) Differential Input Swing Common-Mode Voltage Differential Input Resistance Differential Input Capacitance VDIFFCLK VCMCLK RINCLK CINCLK DVDD 0.2 0.2 4 4 -300 3.4 (Note 3) 2.5 4 7 (Note 3) (Note 3) Clock duty cycle = 50% (Note 3) Clock duty cycle = 50% (Note 3) 2 2.5 1.1 7.5 5.2 Fully differential inputs Self-biased 1.0 to 5.0 1.6 10 3 VP-P V k pF SYMBOL CONDITIONS MIN TYP MAX UNITS CMOS-COMPATIBLE DIGITAL OUTPUTS (D0-D15, DOR, DAV) Digital Output High Voltage Digital Output Low Voltage CLKP - CLKN High CLKP - CLKN Low Effective Aperture Delay Output Data Delay Data Valid Delay Pipeline Latency CLKP Rising Edge to DATA Not Valid CLKP Rising Edge to DATA Guaranteed Valid DATA Setup Time Before Rising DAV DATA Hold Time After Rising DAV POWER SUPPLIES Analog Power-Supply Voltage Digital Output Power-Supply Voltage Analog Power-Supply Current Digital Output Power-Supply Current Power Dissipation AVDD, AVDDA DVDD IAVDD + IAVDDA IDVDD PDISS 3.13 1.7 3.3 1.8 369 31 1275 3.46 1.9 450 42 1561 V V mA mA mW VOH VOL tCLKP tCLKN tAD tDAT tDAV tLATENCY tDNV tDGV tS tH ISOURCE = 200A ISINK = 200A (Note 3) (Note 3) V V ns ns ps ns ns Clock Cycles ns ns ns ns TIMING SPECIFICATIONS (Figures 4, 5), CL = 7.5pF (D0-D15, DOR); CL = 35pF (DAV) Note 1: TA +25C guaranteed by production test, TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C. Note 2: AC parameter measured in a 32,768-point FFT record, where the first 2 bins of the FFT and 2 bins on either side of the carrier are excluded. For SNR and SINAD measurements, bins dominated by production test system noise are excluded. Note 3: Parameter guaranteed by design and characterization. 4 _______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor Typical Operating Characteristics (AVDD = AVDDA = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL = 7.5pF at digital outputs (D0-D15, DOR), CL = 35pF for DAV, fCLK = 100MHz, TA = +25C. Unless otherwise noted, all AC data based on 32k-point FFT records.) FFT PLOT (524,288-POINT DATA RECORD) MAX19588 toc01 MAX19588 FFT PLOT (524,288-POINT DATA RECORD) MAX19588 toc02 SNR/SINAD vs. ANALOG INPUT FREQUENCY (fCLK = 100MHz, AIN = -2dBFS) SNR 80 78 SNR/SINAD (dB) 76 74 72 70 68 SINAD MAX19588 toc03 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) 3 fCLK = 100MHz fIN = 70.164MHz AIN = -1.94dBFS 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 fCLK = 100MHz fIN = 130.001MHz AIN = -1.98dBFS 82 2 3 2 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) 0 20 40 60 80 100 120 140 160 180 fIN (MHz) SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY (fCLK = 100MHz, AIN = -2dBFS) MAX19588toc04 HD2/HD3 vs. ANALOG INPUT FREQUENCY (fCLK = 100MHz, AIN = -2dBFS) MAX19588toc05 SNR vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN = 10MHz) 80 70 SNR (dB, dBFS) 60 50 40 30 SNR (dB) SNR (dBFS) MAX19588toc06 110 105 100 SFDR1/SFDR2 (dBc) 95 90 85 80 SFDR1 75 70 0 20 40 60 SFDR2 -70 HD3 -80 HD2/HD3 (dBc) 90 -90 -100 HD2 -110 20 10 -120 80 100 120 140 160 180 fIN (MHz) 0 20 40 60 80 100 120 140 160 180 fIN (MHz) 0 -80 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT AMPLITUDE (dBFS) SFDR1 vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN = 10MHz) MAX19588toc07 SFDR2 vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN = 10MHz) 120 110 100 90 80 70 60 50 40 30 20 10 0 -80 MAX19588toc08 SNR vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN = 70MHz) 80 70 SNR (dB, dBFS) 60 50 40 30 20 10 0 SNR (dB) MAX19588toc09 120 110 100 SFDR1 (dBc, dBFS) 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT AMPLITUDE (dBFS) SFDR = 90dB REFERENCE LINE SFDR1 (dBc) SFDR1 (dBFS) 90 SNR (dBFS) SFDR2 (dBFS) SFDR2 (dBc, dBFS) SFDR2 (dBc) SFDR = 90dB REFERENCE LINE -70 -60 -50 -40 -30 -20 -10 0 -80 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT AMPLITUDE (dBFS) ANALOG INPUT AMPLITUDE (dBFS) _______________________________________________________________________________________ 5 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 Typical Operating Characteristics (continued) (AVDD = AVDDA = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL = 7.5pF at digital outputs (D0-D15, DOR), CL = 35pF for DAV, fCLK = 100MHz, TA = +25C. Unless otherwise noted, all AC data based on 32k-point FFT records.) SFDR1 vs. ANALOG INPUT AMPLITUDE SFDR2 vs. ANALOG INPUT AMPLITUDE SNR/SINAD vs. SAMPLING FREQUENCY (fCLK = 100MHz, fIN = 70MHz) (fCLK = 100MHz, fIN = 70MHz) (fIN = 10MHz, AIN = -2dBFS) MAX19588toc10 MAX19588toc11 110 100 90 80 70 60 50 40 30 20 10 0 -80 -70 -60 SFDR1 (dBFS) SFDR2 (dBFS) 80 79 78 SNR/SINAD (dB) SNR SFDR1 (dBc, dBFS) SFDR2 (dBc, dBFS) SFDR1 (dBc) SFDR2 (dBc) SFDR = 90dB REFERENCE LINE 77 76 75 74 73 72 71 SINAD SFDR = 90dB REFERENCE LINE -50 -40 -30 -20 -10 0 -80 -70 -60 -50 -40 -30 -20 -10 0 20 30 40 50 60 70 80 90 100 110 ANALOG INPUT AMPLITUDE (dBFS) ANALOG INPUT AMPLITUDE (dBFS) fCLK (MHz) SFDR1/SFDR2 vs. SAMPLING FREQUENCY (fIN = 10MHz, AIN = -2dBFS) MAX19588toc13 HD2/HD3 vs. SAMPLING FREQUENCY (fIN = 10MHz, AIN = -2dBFS) MAX19588toc14 SNR/SINAD vs. SAMPLING FREQUENCY (fIN = 70MHz, AIN = -2dBFS) SNR 80 78 SNR/SINAD (dB) 76 74 72 70 68 SINAD MAX19588toc15 110 105 SFDR1/SFDR2 (dBc) 100 95 90 85 80 75 70 20 30 40 50 60 70 80 SFDR1 SFDR2 -70 -75 -80 HD2/HD3 (dBc) -85 -90 -95 -100 -105 -110 -115 -120 HD2 HD3 82 90 100 110 20 30 40 50 60 70 80 90 100 110 20 30 40 50 60 70 80 90 100 110 fCLK (MHz) fCLK (MHz) fCLK (MHz) SFDR1/SFDR2 vs. SAMPLING FREQUENCY (fIN = 70MHz, AIN = -2dBFS) MAX19588toc16 HD2/HD3 vs. SAMPLING FREQUENCY (fIN = 70MHz, AIN = -2dBFS) MAX19588toc17 SNR/SINAD vs. TEMPERATURE (fCLK = 100MHz, fIN = 10.1MHz, AIN = -2dBFS) SNR 80 SNR/SINAD (dB) MAX19588toc18 105 100 SFDR/SFDR2 (dB) 95 -70 -75 -80 HD2/HD3 (dBc) HD3 82 90 85 80 75 70 20 30 40 50 60 SFDR1 SFDR2 -85 -90 -95 -100 -105 -110 HD2 78 SINAD 76 74 72 20 30 40 50 60 70 80 90 100 110 -40 -15 10 35 60 85 fCLK (MHz) TEMPERATURE (C) 70 80 90 100 110 fCLK (MHz) 6 _______________________________________________________________________________________ MAX19588toc12 120 120 110 100 90 80 70 60 50 40 30 20 10 0 81 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor Typical Operating Characteristics (continued) (AVDD = AVDDA = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL = 7.5pF at digital outputs (D0-D15, DOR), CL = 35pF for DAV, fCLK = 100MHz, TA = +25C. Unless otherwise noted, all AC data based on 32k-point FFT records.) SFDR1/SFDR2 vs. TEMPERATURE (fCLK = 100MHz, fIN = 10.1MHz, AIN = -2dBFS) MAX19588toc19 MAX19588 HD2/HD3 vs. TEMPERATURE (fCLK = 100MHz, fIN = 10.1MHz, AIN = -2dBFS) MAX19588toc20 SFDR2 105 100 SFDR1/SFDR2 (dBc) -85 -90 HD2 -95 -100 -105 -110 HD3 SNR 80 SNR/SINAD (dB) 95 90 85 80 SFDR1 HD2/HD3 (dBc) 78 76 SINAD 74 75 70 -40 -15 10 35 60 85 TEMPERATURE (C) 72 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C) SFDR1/SFDR2 vs. TEMPERATURE (fCLK = 100MHz, fIN = 70.1MHz, AIN = -2dBFS) MAX19588toc22 HD2/HD3 vs. TEMPERATURE (fCLK = 100MHz, fIN = 70.1MHz, AIN = -2dBFS) MAX19588toc23 POWER DISSIPATION vs. TEMPERATURE fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS MAX19588toc24 110 SFDR2 100 SFDR1/SFDR2 (dBc) -70 -75 -80 HD2/HD3 (dBc) -85 -90 -95 -100 HD2 HD3 1300 1290 POWER DISSIPATION (mW) 1280 1270 1260 1250 1240 1230 90 80 SFDR1 70 -105 -110 60 -40 -15 10 35 60 85 TEMPERATURE (C) -115 -40 -15 10 35 60 85 TEMPERATURE (C) -40 -15 10 35 60 85 TEMPERATURE (C) REFERENCE VOLTAGE vs. TEMPERTURE fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS MAX19588toc25 POWER DISSIPTATION vs. ANALOG SUPPLY VOLTAGE 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 3.15 MAX19588toc26 REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE 1.279 1.278 REFERENCE VOLTAGE (V) 1.277 1.276 1.275 1.274 1.273 1.272 1.271 1.270 fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS MAX19588toc27 1.31 1.30 REFERENCE VOLTAGE (V) 1.29 1.28 1.27 1.26 1.25 1.24 -40 1.280 IAVDD + IAVDDA, PDISS (mA, mW) PDISS fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS IAVDD + IAVDDA -15 10 35 60 85 3.20 3.25 3.30 3.35 3.40 3.45 3.15 3.20 3.25 3.30 3.35 3.40 3.45 TEMPERATURE (C) ANALOG SUPPLY VOLTAGE (V) ANALOG SUPPLY VOLTAGE (V) _______________________________________________________________________________________ MAX19588toc21 110 -80 SNR/SINAD vs. TEMPERATURE (fCLK = 100MHz, fIN = 70.1MHz, AIN = -2dBFS) 82 7 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 Typical Operating Characteristics (continued) (AVDD = AVDDA = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL = 7.5pF at digital outputs (D0-D15, DOR), CL = 35pF for DAV, fCLK = 100MHz, TA = +25C. Unless otherwise noted, all AC data based on 32k-point FFT records.) SNR/SINAD vs. ANALOG SUPPLY VOLTAGE MAX19588toc28 SFDR1/SFDR2 vs. ANALOG SUPPLY VOLTAGE MAX19588toc29 HD2/HD3 vs. ANALOG SUPPLY VOLTAGE -75 -80 HD2/HD3 (dBc) -85 HD3 -90 -95 -100 HD2 fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS MAX19588toc30 81 80 79 SNR/SINAD (dB) 78 77 76 SINAD 75 74 73 3.15 3.20 3.25 3.30 3.35 3.40 fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS 110 105 100 SFDR1/SFDR2 (dBc) fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS -70 SNR 95 90 85 80 75 70 SFDR1 SFDR2 -105 -110 3.35 3.40 3.45 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.45 3.15 3.20 3.25 3.30 ANALOG SUPPLY VOLTAGE (V) ANALOG SUPPLY VOLTAGE (V) ANALOG SUPPLY VOLTAGE (V) TWO-TONE SFDR PLOT (32,786-POINT DATA RECORD) MAX19588 toc31 TWO-TONE SFDR PLOT (32,786-POINT DATA RECORD) fCLK = 100MHz fIN1 = 70.102MHz AIN = -8.03dBFS fIN2 = 65.097MHz AIN2 = -8.13dBFS IM3 = -87.7dBc fIN1 fIN2 MAX19588 toc32 0 -20 AMPLITUDE (dBFS) -40 -60 -80 2fIN2 - fIN1 -100 -120 0 5 fIN1 fIN2 fIN2 - fIN1 fCLK = 100MHz fIN1 = 10.098MHz AIN1 = -7.95dBFS fIN2 = 14.871MHz AIN2 = -8.01dBFS IM3 = -104.1dBc 0 -20 AMPLITUDE (dBFS) -40 -60 -80 2fIN1 - fIN2 -100 -120 2fIN2 - fIN1 10 15 20 25 30 35 40 45 50 ANALOG INPUT FREQUENCY (MHz) 0 5 10 15 20 25 30 35 40 45 50 ANALOG INPUT FREQUENCY (MHz) TWO-TONE SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN1 = 10.1MHz, fIN2 = 15.1MHz) 120 110 100 90 80 70 60 50 40 30 20 10 0 120 110 100 90 80 70 60 50 40 30 20 10 0 MAX19588toc33 TWO-TONE SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN1 = 65.1MHz, fIN2 = 70.1MHz) MAX19588toc34 TTSFDR (dBFS) TTSFDR (dBFS) TTSFDR (dBc, dBFS) TTSFDR (dBc, dBFS) TTSFDR (dBc) TTSFDR = 90dB REFERENCE LINE TTSFDR (dBc) TTSFDR = 90dB REFERENCE LINE -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT AMPLITUDE (dBFS) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT AMPLITUDE (dBFS) 8 _______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor Pin Description PIN 1, 2 3, 6-9, 12, 13, 14, 20, 21, 22, 28 4 5 10 11 15, 16, 54 17, 18, 19, 23, 24, 25, 55, 56 26 27 29, 41, 42, 51 30, 31, 52 32 33 34 35 36 37 38 39 40 43 44 45 46 47 48 49 50 NAME AVDDA FUNCTION Auxiliary Analog Supply Voltage. Connect these pins together and connect to AVDD through a 50 series resistor. Converter Ground. Analog, digital, and output-driver grounds are internally connected to the same potential. Connect the converter's exposed paddle (EP) to GND. Differential Clock, Positive Input Terminal Differential Clock, Negative Input Terminal Differential Analog Input, Positive Terminal Differential Analog Input, Negative Terminal No Connection. Do not connect to this pin. Analog Supply Voltage. Provide local bypassing to ground with 0.01F and 0.1F capacitors. Internal Bandgap Reference Output Reference Voltage Input Digital Supply Voltage. Provide local bypassing to ground with 0.01F and 0.1F capacitors. Converter Ground. Digital output-driver ground. Digital CMOS Output Bit 0 (LSB) Digital CMOS Output Bit 1 Digital CMOS Output Bit 2 Digital CMOS Output Bit 3 Digital CMOS Output Bit 4 Digital CMOS Output Bit 5 Digital CMOS Output Bit 6 Digital CMOS Output Bit 7 Digital CMOS Output Bit 8 Digital CMOS Output Bit 9 Digital CMOS Output Bit 10 Digital CMOS Output Bit 11 Digital CMOS Output Bit 12 Digital CMOS Output Bit 13 Digital CMOS Output Bit 14 Digital CMOS Output Bit 15 (MSB) Data Valid Output. This output can be used as a clock control line to drive an external buffer or dataacquisition system. The typical delay time between the falling edge of the converter clock and the rising edge of DAV is 4ns. Data Over-Range Bit. This control line flags an over-/under-range condition in the ADC. If DOR transitions high, an over-/under-range condition was detected. If DOR remains low, the ADC operates within the allowable full-scale range. Exposed Paddle. Must be connected to AGND. MAX19588 AGND CLKP CLKN INP INN N.C. AVDD REFOUT REFIN DVDD DGND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DAV 53 -- DOR EP _______________________________________________________________________________________ 9 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 Detailed Description Figure 1 provides an overview of the MAX19588 architecture. The MAX19588 employs an input track-andhold (T/H) amplifier, which has been optimized for low thermal noise and low distortion. The high-impedance differential inputs to the T/H amplifier (INP and INN) are self-biased at approximately 2.4V, and support a fullscale 2.56VP-P differential input voltage. The output of the T/H amplifier is applied to a multistage pipelined ADC core, which is designed to achieve a very low thermal noise floor and low distortion. A clock buffer receives a differential input clock waveform and generates a low-jitter clock signal for the input T/H. The signal at the analog inputs is sampled at the rising edge of the differential clock waveform. The differential clock inputs (CLKP and CLKN) are highimpedance inputs, are self-biased at 1.6V, and support differential clock waveforms from 1VP-P to 5VP-P. The outputs from the multistage pipelined ADC core are delivered to error correction and formatting logic, which deliver the 16-bit output code in two's-complement format to digital output drivers. The output drivers provide 1.8V CMOS-compatible outputs. signal inputs to the MAX19588 should be AC-coupled and carefully balanced to achieve the best dynamic performance (see Differential, AC-Coupled Analog Inputs in the Applications Information section for more details). ACcoupling of the input signal is required because the MAX19588 inputs are self-biasing as shown in Figure 2. Although the track-and-hold inputs are high impedance, the actual differential input impedance is nominally 10k because of the two 5k resistors connected to the common-mode bias circuitry. Avoid injecting any DC leakage currents into these analog inputs. Exceeding a DC leakage current of 10A shifts the self-biased common-mode level, adversely affecting the converter's performance. On-Chip Reference Circuit The MAX19588 incorporates an on-chip 1.28V, low-drift bandgap reference. This reference potential establishes the full-scale range for the converter, which is nominally 2.56V P-P differential (Figure 3). The internal reference voltage can be monitored by REFOUT. To use the internal reference voltage the reference input (REFIN) must be connected to REFOUT through a 10k resistor. Bypass both pins with separate 1F capacitors to AGND. The MAX19588 also allows an external reference source to be connected to REFIN, enabling the user to overdrive the internal bandgap reference. REFIN accepts a 1.28V 10% input voltage range. Analog Inputs (INP, INN) The signal inputs to the MAX19588 (INP and INN) are balanced differential inputs. This differential configuration provides immunity to common-mode noise coupling and rejection of even-order harmonic terms. The differential CLKP CLKN CLOCK BUFFER CMOS DRIVER AVDD AGND DVDD DAV DOR 16 D0-D15 DGND INP T/H INN PIPELINE ADC CMOS OUTPUT DRIVERS MAX19588 REFERENCE REFOUT REFIN Figure 1. Block Diagram 10 ______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor Clock Inputs (CLKP, CLKN) The differential clock buffer for the MAX19588 has been designed to accept an AC-coupled clock waveform. Like the signal inputs, the clock inputs are self-biasing. In this case, the self-biased potential is 1.6V and each input is connected to the reference potential with a 5k resistor. Consequently, the differential input resistance associated with the clock inputs is 10k. While differential clock signals as low as 0.5VP-P can be used to drive the clock inputs, best dynamic performance is achieved with 1VP-P to 5VP-P clock input voltage levels. Jitter on the clock signal translates directly to jitter (noise) on the sampled signal. Therefore, the clock source must be a very low-jitter (low-phase-noise) source. Additionally, extremely low phase-noise oscillators and bandpass filters should be used to obtain the true AC performance of this converter. See the Differential, AC-Coupled Clock Inputs and Testing the MAX19588 topics in the Applications Information section for additional details on the subject of driving the clock inputs. T/H AMPLIFIER INP TO FIRST QUANTIZER STAGE System Timing Requirements Figure 4 depicts the general timing relationships for the signal input, clock input, data output, and DAV output. Figure 5 shows the detailed timing specifications and signal relationships, as defined in the Electrical Characteristics table. The MAX19588 samples the input signal on the rising edge of the input clock. Output data is valid on the rising edge of the DAV signal, with a 7 clock-cycle data latency. Note that the clock duty cycle should typically be 50% 10% for proper operation. MAX19588 Digital Outputs (D0-D15, DAV, DOR) For best performance, the capacitive loading on the digital outputs of the MAX19588 should be kept as low as possible (< 10pF). Due to the current-limited dataoutput driver of the MAX19588, large capacitive loads increase the rise and fall time of the data and can make it more difficult to register the data into the next IC. The loading capacitance can be kept low by keeping the output traces short and by driving a single CMOS buffer or latch input (as opposed to multiple CMOS inputs). The output data is in two's-complement format, as illustrated in Table 1. Data is valid at the rising edge of DAV (Figures 4, 5). DAV may be used as a clock signal to latch the output data. Note that the DAV output driver is not current limited, hence it allows for higher capacitive loading. The converter's DOR output signal is used to identify over- and under-range conditions. If the input signal exceeds the positive or negative full-scale range for the MAX19588 then DOR will be asserted high. The timing for DOR is identical to the timing for the data outputs, and DOR therefore provides an over-range indication on a sample-by-sample basis. 5k OTA 5k INN T/H AMPLIFIER TO FIRST QUANTIZER STAGE Figure 2. Simplified Analog Input Architecture 2.56VP-P DIFFERENTIAL FSR INP INN -640mV +640mV COMMON-MODE VOLTAGE (2.4V) Figure 3. Full-Scale Voltage Range ______________________________________________________________________________________ 11 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 7 CLOCK-CYCLE LATENCY (tLATENCY) N+1 N N+3 N+7 ANALOG INPUT N+4 N+6 N+5 CLOCK INPUT N+2 D0-D15 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N DAV Figure 4. General System Output Timing Diagram INP INN tAD CLKN N CLKP tDAT D0-D15 N-7 DOR tDAV tS tH N-6 N-5 N-4 tDNV tDGV N+1 N+2 N+3 tCLKP tCLKN DAV ENCODE AT CLKP - CLKN > 0 (RISING EDGE) tCLKP: CLKP - CLKN > 0 tCLKN: CLKP - CLKN < 0 EFFECTIVE APERTURE DELAY tAD: tDAT: DELAY FROM CLKP TO OUTPUT DATA TRANSITION tDAV: tDNV: tDGV: tS: tH : DELAY FROM CLKN TO DATA VALID CLOCK DAV CLKP RISING EDGE TO DATA NOT VALID CLKP RISING EDGE TO DATA GUARANTEED VALID DATA SETUP TIME BEFORE RISING DAV DATA HOLD TIME AFTER RISING DAV Figure 5. Detailed Timing Information for Clock Operation 12 ______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 Table 1. MAX19588 Digital Output Coding INP ANALOG VOLTAGE LEVEL VCM + 0.64V INN ANALOG VOLTAGE LEVEL VCM - 0.64V D15-D0 TWO'S-COMPLEMENT CODE 0111111111111111 (positive full-scale) 0000000000000000 (midscale + ) 1111111111111111 (midscale - ) 1000000000000000 (negative full-scale) VCM VCM VCM - 0.64V VCM + 0.64V Applications Information Differential, AC-Coupled Clock Inputs The clock inputs to the MAX19588 are driven with an AC-coupled differential signal, and best performance is achieved under these conditions. However, it is often the case that the available clock source is single-ended. Figure 6 demonstrates one method for converting a single-ended clock signal into a differential signal with a transformer. In this example, the transformer turns ratio from the primary to secondary side is 1:1.414. The impedance ratio from primary to secondary is the square of the turns ratio, or 1:2. So terminating the sec- ondary side with a 100 differential resistance results in a 50 load looking into the primary side of the transformer. The termination resistor in this example is composed of the series combination of two 50 resistors with their common node AC-coupled to ground. Figure 6 illustrates the secondary side of the transformer to be coupled directly to the clock inputs. Since the clock inputs are self-biasing, the center tap of the transformer must be AC-coupled to ground or left floating. If the center tap of the transformer's secondary side is DC-coupled to ground, it is necessary to add blocking capacitors in series with the clock inputs. AVDD DVDD INP D0-D15 MAX19588 INN 16 0.1F T2-1T-KK81 49.9 BACK-TO-BACK DIODE CLKP CLKN AGND DGND 49.9 0.1F Figure 6. Transformer-Coupled Clock Input Configuration ______________________________________________________________________________________ 13 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor Clock jitter is generally improved if the clock signal has a high slew rate at the time of its zero-crossing. Therefore, if a sinusoidal source is used to drive the clock inputs, the clock amplitude should be as large as possible to maximize the zero-crossing slew rate. The back-to-back Schottky diodes shown in Figure 6 are not required as long as the input signal is held to a differential voltage potential of 3VP-P or less. If a larger amplitude signal is provided (to maximize the zero-crossing slew rate), then the diodes serve to limit the differential signal swing at the clock inputs. Note that all AC specifications for the MAX19588 are measured within this configuration and with an input clock amplitude of approximately 12dBm. Any differential mode noise coupled to the clock inputs translates to clock jitter and degrades the SNR performance of the MAX19588. Any differential mode coupling of the analog input signal into the clock inputs results in harmonic distortion. Consequently, it is important that the clock lines be well isolated from the analog signal input and from the digital outputs. See the Signal Routing section for more discussion on the subject of noise coupling. side of the transformer, the secondary side is terminated with a 100 differential load. This load, in shunt with the differential input resistance of the MAX19588, results in a 100 differential load on the secondary side. It is reasonable to use a larger transformer turns ratio to achieve a larger signal step-up, and this may be desirable to relax the drive requirements for the circuitry driving the MAX19588. However, the larger the turns ratio, the larger the effect of the differential input impedance of the MAX19588 on the primary-referred input impedance. As stated previously, the signal inputs to the MAX19588 must be accurately balanced to achieve the best evenorder distortion performance. One note of caution in relation to transformers is important. Any DC current passed through the primary or secondary windings of a transformer may magnetically bias the transformer core. When this happens the transformer is no longer accurately balanced and a degradation in the distortion of the MAX19588 may be observed. The core must be demagnetized to return to balanced operation. MAX19588 Differential, AC-Coupled Analog Inputs The analog inputs INP and INN are driven with a differential AC-coupled signal. It is important that these inputs be accurately balanced. Any common-mode signal applied to these inputs degrades even-order distortion terms. Therefore, any attempt at driving these inputs in a single-ended fashion will result in significant even-order distortion terms. Figure 7 presents one method for converting a singleended signal to a balanced differential signal using a transformer. The primary-to-secondary turns ratio in this example is 1:1.414. The impedance ratio is the square of the turns ratio, so in this example the impedance ratio is 1:2. To achieve a 50 input impedance at the primary Layer Assignments The MAX19588 EV kit is a 6-layer board, and the assignment of layers is discussed in this context. It is recommended that the ground plane be on a layer between the signal routing layer and the supply routing layer(s). This prevents coupling from the supply lines into the signal lines. The MAX19588 EV kit PC board places the signal lines on the top (component) layer and the ground plane on layer 2. Any region on the top layer not devoted to signal routing is filled with the ground plane with vias to layer 2. Layers 3 and 4 are devoted to supply routing, layer 5 is another ground plane, and layer 6 is used for the placement of additional components and for additional signal routing. AVDD DVDD POSITIVE TERMINAL 0.1F ADT2-1T T1-1T-KK81 49.9 INP D0-D15 MAX19588 49.9 16 INN 0.1F CLKP CLKN AGND DGND Figure 7. Transformer-Coupled Analog Input Configuration with Primary-Side Balun Transformer 14 ______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor A four-layer implementation is also feasible using layer 1 for signal lines, layer 2 as a ground plane, layer 3 for supply routing, and layer 4 for additional signal routing. However, care must be taken to ensure that the clock and signal lines are isolated from each other and from the supply lines. traces should not be removed so that the digital groundreturn currents have an uninterrupted path back to the bypass capacitors. MAX19588 Grounding The practice of providing a split ground plane in an attempt to confine digital ground-return currents has often been recommended in ADC application literature. However, for converters such as the MAX19588 it is strongly recommended to employ a single, uninterrupted ground plane. The MAX19588 EV kit achieves excellent dynamic performance with such a ground plane. The exposed paddle of the MAX19588 should be soldered directly to a ground pad on layer 1 with vias to the ground plane on layer 2. This provides excellent electrical and thermal connections to the PC board. Signal Routing To preserve good even-order distortion, the signal lines (those traces feeding the INP and INN inputs) must be carefully balanced. To accomplish this, the signal traces should be made as symmetric as possible, meaning that each of the two signal traces should be the same length and should see the same parasitic environment. As mentioned previously, the signal lines must be isolated from the supply lines to prevent coupling from the supplies to the inputs. This is accomplished by making the necessary layer assignments as described in the previous section. Additionally, it is crucial that the clock lines be isolated from the signal lines. On the MAX19588 EV kit this is done by routing the clock lines on the bottom layer (layer 6). The clock lines then connect to the ADC through vias placed in close proximity to the device. The clock lines are isolated from the supply lines as well by virtue of the ground plane on layer 5. As with all high-speed designs, digital output traces should be kept as short as possible to minimize capacitive loading. The ground plane on layer 2 beneath these Supply Bypassing The MAX19588 EV kit uses 220F capacitors (and smaller values such as 47F and 2F) on power-supply lines AVDD, AVDDA, and DVDD to provide low-frequency bypassing. The loss (series resistance) associated with these capacitors is beneficial in eliminating high-Q supply resonances. Ferrite beads are also used on each of the power-supply lines to enhance supply bypassing (Figure 8). BYPASSING--ADC LEVEL AVDD DVDD AVDD BYPASSING--BOARD LEVEL FERRITE BEAD 0.01F 0.1F AGND 50 AVDD AVDDA 0.1F 0.01F 2F 47F 220F ANALOG POWERSUPPLY SOURCE DGND DVDD D0-D15 DVDD FERRITE BEAD MAX19588 16 2F 47F 220F DIGITAL POWERSUPPLY SOURCE AGND DGND Figure 8. Grounding, Bypassing, and Decoupling Recommendations for the MAX19588 ______________________________________________________________________________________ 15 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 AGILENT 8644B SIGNAL PATH BANDPASS FILTER 10dB 3dB PAD BOTH SIGNAL GENERATORS ARE PHASE-LOCKED AGILENT 8644B MAX19588 FFT PLOT (542,288-POINT DATA RECORD) 0 -20 AMPLITUDE (dBFS) -40 -60 -80 3 -100 -120 2 fCLK = 100MHz fIN = 67.6MHz AIN = -1.98dBFS CLOCK PATH BANDPASS FILTER Figure 9a. Standard High-Speed ADC Test Setup (Simplified Diagram) FFT PLOT (524,288-POINT DATA RECORD) 0 -20 AMPLITUDE (dBFS) -40 -60 -80 3 -100 -120 -140 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) 2 fCLK = 100MHz fIN = 70.1MHz AIN = -2.04dBFS -140 0 5 10 15 20 25 30 35 40 45 ANALOG FREQUENCY (MHz) Figure 9c. 68MHz FFT with Standard High-Speed ADC Test Setup Testing the MAX19588 The MAX19588 has a very low thermal noise floor (-82dBFS) and very low jitter (< 100fs). As a consequence, test system limitations can easily obscure the performance of the ADC. Figure 9a is a block diagram of a conventional high-speed ADC test system. The input signal and the clock source are generated by low-phase-noise synthesizers (e.g., HP/Agilent 8644B). Bandpass filters in both the signal and the clock paths then attenuate noise and harmonic components. Figure 9b shows the resulting power spectrum, which results from this setup for a 70MHz input tone and a 100Msps clock. Note the substantial lift in the noise floor near the carrier. The bandwidth of this particular noise-floor lift near the carrier corresponds to the bandwidth of the filter in the input signal path. Figure 9c illustrates the impact on the spectrum if the input frequency is shifted away from the center frequency of the input signal filter. Note that the fundamental tone has moved, but the noise-floor lift remains in the same location. This is evidence of the validity of the claim that the lift in the noise floor is due to the test system and not the ADC. In this figure, the magnitude of the lift in the noise floor increased relative to the previous figure because the signal is located on the skirt of the filter and the signal amplitude had to be increased to obtain a signal near full scale. Figure 9b. 70MHz FFT with Standard High-Speed ADC Test Setup Combinations of small value (0.01F and 0.1F), lowinductance surface-mount capacitors should be placed at each supply pin or each grouping of supply pins to attenuate high-frequency supply noise. Place these capacitors on the top side of the board and as close to the converter as possible with short connections to the ground plane. Supply/Clock Sequencing Power up the MAX19588 (any sequence will be acceptible) and then apply the clock. If the clock is present before the MAX19588 is powered up, ensure that DVDD is brought up first followed by AVDD. 16 ______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 AGILENT 8644B SIGNAL PATH VARIABLE BANDPASS ATTENUATOR FILTER REF PLL SIGNAL TUNE 10dB VCXO 3dB PAD MAX19588 LOW-NOISE PLL BOTH SIGNAL GENERATORS ARE PHASE-LOCKED AGILENT 8644B CLOCK PATH BANDPASS FILTER 10dB VCXO REF PLL SIGNAL TUNE LOW-NOISE PLL Figure 9d. Improved Test System Employing Narrowband PLLs (Simplified Diagram) FFT PLOT (524,288-POINT DATA RECORD) 0 -20 AMPLITUDE (dBFS) -40 SNR (dB) -60 -80 -100 -120 -140 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) 3 2 fCLK = 100MHz fIN = 70.164MHz AIN = -1.94dBFS 110 105 100 95 90 85 80 75 70 65 60 10 100 RMS JITTER (fs) 1000 INPUT FREQUENCY = 140MHz INPUT FREQUENCY = 70MHz SNR vs. RMS JITTER PERFORMANCE Figure 9e. 70MHz FFT with Improved High-Speed ADC Test Setup Figure 9f. SNR vs. System Jitter Performance Graph To truly reveal the performance of the MAX19588, the test system performance must be improved substantially. Figure 9d depicts such an improved test system. In this system, the synthesizers provide reference inputs to two dedicated low-noise phase-locked loops (PLLs), one centered at approximately 100MHz (for the clock path) and the other centered at 70MHz (for the signal path). The oscillators in these PLLs are very low-noise oscillators, and the PLLs act as extremely narrow bandwidth filters (on the order of 20Hz) to attenuate the noise of the synthesizers. The system provides a total system jitter on the order of 20fs. Note that while the low-noise oscillators could be used by themselves without being locked to their respective signal sources, this would result in FFTs that are not coherent and which would require windowing. Figure 9e is an FFT plot of the spectrum obtained when the improved test system is employed. The noise-floor lift in the vicinity of the carrier is now almost completely eliminated. The SNR associated with this FFT is 79dB, whereas the SNR obtained using the standard test system is 77.2dB. Figure 9f demonstrates the impact of test system jitter on measured SNR. The figure plots SNR due to test system jitter only, neglecting all other sources of noise, for two different input frequencies. For example, note that for a 70MHz input frequency a test system jitter number of 100fs results in an SNR (due to the test system alone) of about 87dB. In the case of the MAX19588, which has a -82dBFS noise floor, this is not an inconsequential amount of additional noise. 17 ______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 In conclusion, careful attention must be paid to both the input signal source and the clock signal source, if the true performance of the MAX19588 is to be properly characterized. Dedicated PLLs with low-noise VCOs, such as those used in Figure 9d, are capable of providing signals with the required low jitter performance. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first four harmonics (HD2 through HD5), and the DC offset. SNR = 20 x log (SIGNALRMS / NOISERMS) Parameter Definitions Offset Error Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally, the midscale MAX19588 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Spurious-Free Dynamic Range (SFDR1 and SFDR2) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR1 reflects the MAX19588 spurious performance based on worst 2ndor 3rd-order harmonic distortion. SFDR2 is defined by the worst spurious component excluding 2nd- and 3rdorder harmonic spurs and DC offset. Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally, the positive full-scale MAX19588 transition occurs at 1.5 LSBs below positive full scale, and the negative fullscale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points. Two-Tone Spurious-Free Dynamic Range (TTSFDR) Two-tone SFDR is the ratio of the full scale of the converter to the RMS value of the peak spurious component. The peak spurious component can be related to the intermodulation distortion components, but does not have to be. Two-tone SFDR for the MAX19588 is expressed in dBFS. Small-Signal Noise Floor (SSNF) Small-signal noise floor is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude of less than -35dBFS. This parameter captures the thermal and quantization noise characteristics of the data converter and can be used to help calculate the overall noise figure of a digital receiver signal path. 3rd-Order Intermodulation (IM3) IM3 is the power of the largest 3rd-order intermodulation product relative to the input power of either of the input tones f IN1 and f IN2 . The individual input tone power levels are set to -8dBFS for the MAX19588. The 3rd-order intermodulation products are 2 x fIN1 - fIN2 and 2 x fIN2 - fIN1. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR[max] = 6.02 x N + 1.76 Aperture Jitter Aperture jitter (tAJ) represents the sample-to-sample variation in the aperture delay specification. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 5). 18 ______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 56L THIN QFN.EPS MAX19588 PACKAGE OUTLINE 56L THIN QFN, 8x8x0.8mm 21-0135 E 1 2 PACKAGE OUTLINE 56L THIN QFN, 8x8x0.8mm 21-0135 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. FREED Freed |
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